The memory cells in a highly integrated memory device may take a long time to test. Therefore, parallel bit testing methods have been developed for testing the memory cells by simultaneously writing data to and reading data from a plurality of memory cells. By simultaneously writing to and reading from multiple memory cells, test time can be reduced. See for example, U.S. Pat. No. 5,568,434 to Jeon entitled "Multi-Bit Testing Circuit for Semiconductor Memory Device".
Referring to FIG. 1, a conventional memory device includes a memory cell array 101, input and output lines IO1/IO1 through IOn/IOn, data input and output lines DIO1/DIO1 through DIOn/DIOn, column select lines CSL11 through CSL1n and CSL21 through CSL2n, and a column decoder 103. The column select lines CSL11 through CSL1n and CSL21 through CSL2n connect the bit lines of the memory cell array 101 to the respective input and output lines.
In a parallel bit test mode, the input and output lines IO1/IO1 through IOn/IOn are connected to the data input and output lines DIO1/DIO1 through DIOn/DIOn. Data is simultaneously written to and read from the memory cells through the input and output lines and the data input and output lines. For example, when there are 32 input and output lines and 32 data input and output lines, 32 bits of data may be simultaneously written to and read from the memory cells. The column select lines CSL11 through CSL1n and CSL21 through CSL2n are sequentially activated by the column decoder 103 during the read and write cycles of the parallel bit test mode.
Unfortunately, in a highly integrated memory device, excessive writing and reading time may still be used, even though the parallel bit test method is used. Accordingly, there continues to be a need to allow further reduction in testing time.